Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits

Buses of CMOS VLSI Circuits Harish Kriplani, Farid Najm and Ibrahim Hajj Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign Abstract: This paper summarizes the main developments of our on going study at University of Illinois on the maximum voltage drop estimation in power and ground buses of CMOS VLSI circuits. Voltage drops occurring in the supply lines depend upon the speci c input patterns applied to the circuit and it is prohibitively expensive to enumerate all possible input patterns. Our proposed solution methodology consists of two parts. In the rst part, maximum current waveforms at every contact point in the circuit are estimated by the linear time, pattern independent algorithm, called iMax. The algorithm is extremely e cient in time as well as space, and produces good results for most circuits. The accuracy of the results obtained from the iMax algorithm can be further improved by resolving the signal correlations that exist inside a circuit. In the second part of the voltage drop estimation process, we iteratively resolve these correlations by a novel partial input enumeration (PIE) technique and thus improve the bounds on the maximum voltage drop. We establish with extensive experimental results that these algorithms are extremely e cient and are applicable to VLSI circuits.